Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems

Yukio MITSUYAMA; Motoki KIMURA; Takao ONOYE; Isao SHIRAKAWA

doi:10.1093/ietfec/e88-a.4.899

Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems

Yukio MITSUYAMA, Motoki KIMURA, Takao ONOYE, Isao SHIRAKAWA

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VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.899-906

Publication Date: 2005/04/01

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DOI: 10.1093/ietfec/e88-a.4.899

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

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Yukio MITSUYAMA, Motoki KIMURA, Takao ONOYE, Isao SHIRAKAWA, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 4, pp. 899-906, April 2005, doi: 10.1093/ietfec/e88-a.4.899.
Abstract: VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.899/_p

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@ARTICLE{e88-a_4_899,
author={Yukio MITSUYAMA, Motoki KIMURA, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems},
year={2005},
volume={E88-A},
number={4},
pages={899-906},
abstract={VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.},
keywords={},
doi={10.1093/ietfec/e88-a.4.899},
ISSN={},
month={April},}

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TY - JOUR
TI - Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 899
EP - 906
AU - Yukio MITSUYAMA
AU - Motoki KIMURA
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 2005
DO - 10.1093/ietfec/e88-a.4.899
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.
ER -