A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

Mehdi BANIHASHEMI; Khayrollah HADIDI; Abdollah KHOEI

doi:10.1093/ietfec/e88-a.4.996

A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

Mehdi BANIHASHEMI, Khayrollah HADIDI, Abdollah KHOEI

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A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm², respectively. ADC was extensively simulated using Hspice to verify the desired performance.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.996-1006

Publication Date: 2005/04/01

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DOI: 10.1093/ietfec/e88-a.4.996

Type of Manuscript: PAPER

Category: Analog Signal Processing

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Mehdi BANIHASHEMI, Khayrollah HADIDI, Abdollah KHOEI, "A Low-Power, Small-Size 10-Bit Successive-Approximation ADC" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 4, pp. 996-1006, April 2005, doi: 10.1093/ietfec/e88-a.4.996.
Abstract: A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm², respectively. ADC was extensively simulated using Hspice to verify the desired performance.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.996/_p

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@ARTICLE{e88-a_4_996,
author={Mehdi BANIHASHEMI, Khayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low-Power, Small-Size 10-Bit Successive-Approximation ADC},
year={2005},
volume={E88-A},
number={4},
pages={996-1006},
abstract={A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm², respectively. ADC was extensively simulated using Hspice to verify the desired performance.},
keywords={},
doi={10.1093/ietfec/e88-a.4.996},
ISSN={},
month={April},}

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TY - JOUR
TI - A Low-Power, Small-Size 10-Bit Successive-Approximation ADC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 996
EP - 1006
AU - Mehdi BANIHASHEMI
AU - Khayrollah HADIDI
AU - Abdollah KHOEI
PY - 2005
DO - 10.1093/ietfec/e88-a.4.996
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm², respectively. ADC was extensively simulated using Hspice to verify the desired performance.
ER -