This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.
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Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, Masanori HASHIMOTO, "Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3560-3568, December 2006, doi: 10.1093/ietfec/e89-a.12.3560.
Abstract: This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3560/_p
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@ARTICLE{e89-a_12_3560,
author={Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design},
year={2006},
volume={E89-A},
number={12},
pages={3560-3568},
abstract={This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3560},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3560
EP - 3568
AU - Toshiki KANAMOTO
AU - Tatsuhiko IKEDA
AU - Akira TSUCHIYA
AU - Hidetoshi ONODERA
AU - Masanori HASHIMOTO
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3560
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.
ER -