Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Yang SONG; Zhenyu LIU; Satoshi GOTO; Takeshi IKENAGA

doi:10.1093/ietfec/e89-a.4.979

Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Yang SONG, Zhenyu LIU, Satoshi GOTO, Takeshi IKENAGA

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Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.979-988

Publication Date: 2006/04/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.4.979

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)

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Yang SONG, Zhenyu LIU, Satoshi GOTO, Takeshi IKENAGA, "Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 4, pp. 979-988, April 2006, doi: 10.1093/ietfec/e89-a.4.979.
Abstract: Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.979/_p

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@ARTICLE{e89-a_4_979,
author={Yang SONG, Zhenyu LIU, Satoshi GOTO, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC},
year={2006},
volume={E89-A},
number={4},
pages={979-988},
abstract={Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).},
keywords={},
doi={10.1093/ietfec/e89-a.4.979},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 979
EP - 988
AU - Yang SONG
AU - Zhenyu LIU
AU - Satoshi GOTO
AU - Takeshi IKENAGA
PY - 2006
DO - 10.1093/ietfec/e89-a.4.979
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).
ER -