A New Energy<cd0215f.gif>Delay-Aware Flip-Flop

Inhwa JUNG; Moo-young KIM; Dongsuk SHIN; Seon Wook KIM; Chulwoo KIM

doi:10.1093/ietfec/e89-a.6.1552

A New EnergyDelay-Aware Flip-Flop

Inhwa JUNG, Moo-young KIM, Dongsuk SHIN, Seon Wook KIM, Chulwoo KIM

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This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.6 pp.1552-1557

Publication Date: 2006/06/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.6.1552

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))

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Inhwa JUNG, Moo-young KIM, Dongsuk SHIN, Seon Wook KIM, Chulwoo KIM, "A New EnergyDelay-Aware Flip-Flop" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 6, pp. 1552-1557, June 2006, doi: 10.1093/ietfec/e89-a.6.1552.
Abstract: This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.6.1552/_p

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@ARTICLE{e89-a_6_1552,
author={Inhwa JUNG, Moo-young KIM, Dongsuk SHIN, Seon Wook KIM, Chulwoo KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New EnergyDelay-Aware Flip-Flop},
year={2006},
volume={E89-A},
number={6},
pages={1552-1557},
abstract={This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.},
keywords={},
doi={10.1093/ietfec/e89-a.6.1552},
ISSN={1745-1337},
month={June},}

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TY - JOUR
TI - A New EnergyDelay-Aware Flip-Flop
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1552
EP - 1557
AU - Inhwa JUNG
AU - Moo-young KIM
AU - Dongsuk SHIN
AU - Seon Wook KIM
AU - Chulwoo KIM
PY - 2006
DO - 10.1093/ietfec/e89-a.6.1552
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2006
AB - This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.
ER -