A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture

Hiroki SAKURAI; Shigeto TANAKA; Yasuhiro SUGIMOTO

doi:10.1093/ietfec/e90-a.10.2272

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture

Hiroki SAKURAI, Shigeto TANAKA, Yasuhiro SUGIMOTO

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This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.10 pp.2272-2279

Publication Date: 2007/10/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.10.2272

Type of Manuscript: PAPER

Category: Analog Signal Processing

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Hiroki SAKURAI, Shigeto TANAKA, Yasuhiro SUGIMOTO, "A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 10, pp. 2272-2279, October 2007, doi: 10.1093/ietfec/e90-a.10.2272.
Abstract: This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.10.2272/_p

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@ARTICLE{e90-a_10_2272,
author={Hiroki SAKURAI, Shigeto TANAKA, Yasuhiro SUGIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture},
year={2007},
volume={E90-A},
number={10},
pages={2272-2279},
abstract={This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.},
keywords={},
doi={10.1093/ietfec/e90-a.10.2272},
ISSN={1745-1337},
month={October},}

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TY - JOUR
TI - A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2272
EP - 2279
AU - Hiroki SAKURAI
AU - Shigeto TANAKA
AU - Yasuhiro SUGIMOTO
PY - 2007
DO - 10.1093/ietfec/e90-a.10.2272
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2007
AB - This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.
ER -