Opposite-Phase Clock Tree for Peak Current Reduction

Yow-Tyng NIEH; Shih-Hsu HUANG; Sheng-Yu HSU

doi:10.1093/ietfec/e90-a.12.2727

Opposite-Phase Clock Tree for Peak Current Reduction

Yow-Tyng NIEH, Shih-Hsu HUANG, Sheng-Yu HSU

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Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2727-2735

Publication Date: 2007/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.12.2727

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Circuit Synthesis

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Yow-Tyng NIEH, Shih-Hsu HUANG, Sheng-Yu HSU, "Opposite-Phase Clock Tree for Peak Current Reduction" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2727-2735, December 2007, doi: 10.1093/ietfec/e90-a.12.2727.
Abstract: Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2727/_p

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@ARTICLE{e90-a_12_2727,
author={Yow-Tyng NIEH, Shih-Hsu HUANG, Sheng-Yu HSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Opposite-Phase Clock Tree for Peak Current Reduction},
year={2007},
volume={E90-A},
number={12},
pages={2727-2735},
abstract={Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2727},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Opposite-Phase Clock Tree for Peak Current Reduction
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2727
EP - 2735
AU - Yow-Tyng NIEH
AU - Shih-Hsu HUANG
AU - Sheng-Yu HSU
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2727
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.
ER -