Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram

Hiroaki TANAKA; Yoshinori TAKEUCHI; Keishi SAKANUSHI; Masaharu IMAI; Hiroki TAGAWA; Yutaka OTA; Nobu MATSUMOTO

doi:10.1093/ietfec/e90-a.12.2800

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram

Hiroaki TANAKA, Yoshinori TAKEUCHI, Keishi SAKANUSHI, Masaharu IMAI, Hiroki TAGAWA, Yutaka OTA, Nobu MATSUMOTO

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SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2800-2809

Publication Date: 2007/12/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.12.2800

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: System Level Design

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Hiroaki TANAKA, Yoshinori TAKEUCHI, Keishi SAKANUSHI, Masaharu IMAI, Hiroki TAGAWA, Yutaka OTA, Nobu MATSUMOTO, "Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2800-2809, December 2007, doi: 10.1093/ietfec/e90-a.12.2800.
Abstract: SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2800/_p

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@ARTICLE{e90-a_12_2800,
author={Hiroaki TANAKA, Yoshinori TAKEUCHI, Keishi SAKANUSHI, Masaharu IMAI, Hiroki TAGAWA, Yutaka OTA, Nobu MATSUMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram},
year={2007},
volume={E90-A},
number={12},
pages={2800-2809},
abstract={SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2800},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2800
EP - 2809
AU - Hiroaki TANAKA
AU - Yoshinori TAKEUCHI
AU - Keishi SAKANUSHI
AU - Masaharu IMAI
AU - Hiroki TAGAWA
AU - Yutaka OTA
AU - Nobu MATSUMOTO
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2800
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.
ER -