Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs

Kohei HOSOKAWA; Katsunori TANAKA; Yuichi NAKAMURA

doi:10.1093/ietfec/e90-a.12.2810

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs

Kohei HOSOKAWA, Katsunori TANAKA, Yuichi NAKAMURA

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FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2810-2817

Publication Date: 2007/12/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.12.2810

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: System Level Design

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Kohei HOSOKAWA, Katsunori TANAKA, Yuichi NAKAMURA, "Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2810-2817, December 2007, doi: 10.1093/ietfec/e90-a.12.2810.
Abstract: FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2810/_p

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@ARTICLE{e90-a_12_2810,
author={Kohei HOSOKAWA, Katsunori TANAKA, Yuichi NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs},
year={2007},
volume={E90-A},
number={12},
pages={2810-2817},
abstract={FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2810},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2810
EP - 2817
AU - Kohei HOSOKAWA
AU - Katsunori TANAKA
AU - Yuichi NAKAMURA
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2810
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.
ER -