Implementations of Low-Cost Hardware Sharing Architectures for Fast 8<cd0215f.gif>8 and 4<cd0215f.gif>4 Integer Transforms in H.264/AVC

Chih-Peng FAN; Yu-Lian LIN

doi:10.1093/ietfec/e90-a.2.511

Implementations of Low-Cost Hardware Sharing Architectures for Fast 88 and 44 Integer Transforms in H.264/AVC

Chih-Peng FAN, Yu-Lian LIN

Full Text Views

0

Share
Cite this

Summary :

In this paper, novel hardware sharing architectures are proposed for realizations of fast 44 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.2 pp.511-516

Publication Date: 2007/02/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.2.511

Type of Manuscript: LETTER

Category: Digital Signal Processing

Cite this

Copy

Chih-Peng FAN, Yu-Lian LIN, "Implementations of Low-Cost Hardware Sharing Architectures for Fast 88 and 44 Integer Transforms in H.264/AVC" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 2, pp. 511-516, February 2007, doi: 10.1093/ietfec/e90-a.2.511.
Abstract: In this paper, novel hardware sharing architectures are proposed for realizations of fast 44 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.2.511/_p

Copy

@ARTICLE{e90-a_2_511,
author={Chih-Peng FAN, Yu-Lian LIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Implementations of Low-Cost Hardware Sharing Architectures for Fast 88 and 44 Integer Transforms in H.264/AVC},
year={2007},
volume={E90-A},
number={2},
pages={511-516},
abstract={In this paper, novel hardware sharing architectures are proposed for realizations of fast 44 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.},
keywords={},
doi={10.1093/ietfec/e90-a.2.511},
ISSN={1745-1337},
month={February},}

Copy

TY - JOUR
TI - Implementations of Low-Cost Hardware Sharing Architectures for Fast 88 and 44 Integer Transforms in H.264/AVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 511
EP - 516
AU - Chih-Peng FAN
AU - Yu-Lian LIN
PY - 2007
DO - 10.1093/ietfec/e90-a.2.511
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2007
AB - In this paper, novel hardware sharing architectures are proposed for realizations of fast 44 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.
ER -