Diversification of Processors Based on Redundancy in Instruction Set

Shuichi ICHIKAWA; Takashi SAWADA; Hisashi HATA

doi:10.1093/ietfec/e91-a.1.211

Diversification of Processors Based on Redundancy in Instruction Set

Shuichi ICHIKAWA, Takashi SAWADA, Hisashi HATA

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By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.1 pp.211-220

Publication Date: 2008/01/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.1.211

Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)

Category: Implementation

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Shuichi ICHIKAWA, Takashi SAWADA, Hisashi HATA, "Diversification of Processors Based on Redundancy in Instruction Set" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 1, pp. 211-220, January 2008, doi: 10.1093/ietfec/e91-a.1.211.
Abstract: By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.1.211/_p

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@ARTICLE{e91-a_1_211,
author={Shuichi ICHIKAWA, Takashi SAWADA, Hisashi HATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Diversification of Processors Based on Redundancy in Instruction Set},
year={2008},
volume={E91-A},
number={1},
pages={211-220},
abstract={By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.},
keywords={},
doi={10.1093/ietfec/e91-a.1.211},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - Diversification of Processors Based on Redundancy in Instruction Set
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 211
EP - 220
AU - Shuichi ICHIKAWA
AU - Takashi SAWADA
AU - Hisashi HATA
PY - 2008
DO - 10.1093/ietfec/e91-a.1.211
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2008
AB - By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.
ER -