Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications

Ching-Yuan YANG; Ken-Hao CHANG

doi:10.1093/ietfec/e91-a.1.409

Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications

Ching-Yuan YANG, Ken-Hao CHANG

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An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.1 pp.409-412

Publication Date: 2008/01/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.1.409

Type of Manuscript: LETTER

Category: VLSI Design Technology and CAD

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Ching-Yuan YANG, Ken-Hao CHANG, "Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 1, pp. 409-412, January 2008, doi: 10.1093/ietfec/e91-a.1.409.
Abstract: An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.1.409/_p

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@ARTICLE{e91-a_1_409,
author={Ching-Yuan YANG, Ken-Hao CHANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications},
year={2008},
volume={E91-A},
number={1},
pages={409-412},
abstract={An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.},
keywords={},
doi={10.1093/ietfec/e91-a.1.409},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 409
EP - 412
AU - Ching-Yuan YANG
AU - Ken-Hao CHANG
PY - 2008
DO - 10.1093/ietfec/e91-a.1.409
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2008
AB - An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.
ER -