Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method

Masakatsu NISHIGAKI; Nobuyuki TANAKA; Hideki ASAI

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Masakatsu NISHIGAKI, Nobuyuki TANAKA, Hideki ASAI, "Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method" in IEICE TRANSACTIONS on Fundamentals, vol. E75-A, no. 3, pp. 347-351, March 1992, doi: .
Abstract: For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e75-a_3_347/_p

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@ARTICLE{e75-a_3_347,
author={Masakatsu NISHIGAKI, Nobuyuki TANAKA, Hideki ASAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method},
year={1992},
volume={E75-A},
number={3},
pages={347-351},
abstract={For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 347
EP - 351
AU - Masakatsu NISHIGAKI
AU - Nobuyuki TANAKA
AU - Hideki ASAI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1992
AB - For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.
ER -