A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning

Vijaya Gopal BANDI; Hideki ASAI

A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning

Vijaya Gopal BANDI, Hideki ASAI

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This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.4 pp.657-660

Publication Date: 1993/04/25

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Type of Manuscript: LETTER

Category: Neural Networks

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Vijaya Gopal BANDI, Hideki ASAI, "A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning" in IEICE TRANSACTIONS on Fundamentals, vol. E76-A, no. 4, pp. 657-660, April 1993, doi: .
Abstract: This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e76-a_4_657/_p

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@ARTICLE{e76-a_4_657,
author={Vijaya Gopal BANDI, Hideki ASAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning},
year={1993},
volume={E76-A},
number={4},
pages={657-660},
abstract={This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 657
EP - 660
AU - Vijaya Gopal BANDI
AU - Hideki ASAI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 1993
AB - This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.
ER -