Low Temperature Coefficient CMOS Voltage Reference Circuits

Katsuji KIMURA

Low Temperature Coefficient CMOS Voltage Reference Circuits

Katsuji KIMURA

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Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.2 pp.398-402

Publication Date: 1994/02/25

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Type of Manuscript: Special Section LETTER (Special Section on High-Performance MOS Analog Circuits)

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Katsuji KIMURA, "Low Temperature Coefficient CMOS Voltage Reference Circuits" in IEICE TRANSACTIONS on Fundamentals, vol. E77-A, no. 2, pp. 398-402, February 1994, doi: .
Abstract: Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e77-a_2_398/_p

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@ARTICLE{e77-a_2_398,
author={Katsuji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Temperature Coefficient CMOS Voltage Reference Circuits},
year={1994},
volume={E77-A},
number={2},
pages={398-402},
abstract={Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Low Temperature Coefficient CMOS Voltage Reference Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 398
EP - 402
AU - Katsuji KIMURA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1994
AB - Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.
ER -