Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System

Katsuyoshi MIURA; Koji NAKAMAE; Hiromu FUJIOKA

Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System

Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA

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An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.3 pp.539-545

Publication Date: 1994/03/25

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Type of Manuscript: PAPER

Category: Computer Aided Design (CAD)

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Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, "Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System" in IEICE TRANSACTIONS on Fundamentals, vol. E77-A, no. 3, pp. 539-545, March 1994, doi: .
Abstract: An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e77-a_3_539/_p

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@ARTICLE{e77-a_3_539,
author={Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System},
year={1994},
volume={E77-A},
number={3},
pages={539-545},
abstract={An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 539
EP - 545
AU - Katsuyoshi MIURA
AU - Koji NAKAMAE
AU - Hiromu FUJIOKA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1994
AB - An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.
ER -