Reclocking Controllers for Minimum Execution Time

Pradip JHA; Sri PARAMESWARAN; Nikil DUTT

Reclocking Controllers for Minimum Execution Time

Pradip JHA, Sri PARAMESWARAN, Nikil DUTT

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In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1715-1721

Publication Date: 1995/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Pradip JHA, Sri PARAMESWARAN, Nikil DUTT, "Reclocking Controllers for Minimum Execution Time" in IEICE TRANSACTIONS on Fundamentals, vol. E78-A, no. 12, pp. 1715-1721, December 1995, doi: .
Abstract: In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e78-a_12_1715/_p

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@ARTICLE{e78-a_12_1715,
author={Pradip JHA, Sri PARAMESWARAN, Nikil DUTT, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reclocking Controllers for Minimum Execution Time},
year={1995},
volume={E78-A},
number={12},
pages={1715-1721},
abstract={In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Reclocking Controllers for Minimum Execution Time
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1715
EP - 1721
AU - Pradip JHA
AU - Sri PARAMESWARAN
AU - Nikil DUTT
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1995
AB - In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.
ER -