Memory Sharing Processor Array (MSPA) Architecture

Dongju LI; Hiroaki KUNIEDA

Memory Sharing Processor Array (MSPA) Architecture

Dongju LI, Hiroaki KUNIEDA

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In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.12 pp.2086-2096

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Dongju LI, Hiroaki KUNIEDA, "Memory Sharing Processor Array (MSPA) Architecture" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 12, pp. 2086-2096, December 1996, doi: .
Abstract: In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e79-a_12_2086/_p

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@ARTICLE{e79-a_12_2086,
author={Dongju LI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Memory Sharing Processor Array (MSPA) Architecture},
year={1996},
volume={E79-A},
number={12},
pages={2086-2096},
abstract={In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Memory Sharing Processor Array (MSPA) Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2086
EP - 2096
AU - Dongju LI
AU - Hiroaki KUNIEDA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1996
AB - In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.
ER -