Automatic Synthesis of a Serial Input Multiprocessor Array

Dongji LI; Hiroaki KUNIEDA

Automatic Synthesis of a Serial Input Multiprocessor Array

Dongji LI, Hiroaki KUNIEDA

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Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.12 pp.2097-2105

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Dongji LI, Hiroaki KUNIEDA, "Automatic Synthesis of a Serial Input Multiprocessor Array" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 12, pp. 2097-2105, December 1996, doi: .
Abstract: Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e79-a_12_2097/_p

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@ARTICLE{e79-a_12_2097,
author={Dongji LI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Automatic Synthesis of a Serial Input Multiprocessor Array},
year={1996},
volume={E79-A},
number={12},
pages={2097-2105},
abstract={Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Automatic Synthesis of a Serial Input Multiprocessor Array
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2097
EP - 2105
AU - Dongji LI
AU - Hiroaki KUNIEDA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1996
AB - Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.
ER -