DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses

Nobuhiko SUGINO; Hironobu MIYAZAKI; Akinori NISHIHARA

DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses

Nobuhiko SUGINO, Hironobu MIYAZAKI, Akinori NISHIHARA

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Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.12 pp.2562-2571

Publication Date: 1997/12/25

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Category: Digital Signal Processing

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Nobuhiko SUGINO, Hironobu MIYAZAKI, Akinori NISHIHARA, "DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses" in IEICE TRANSACTIONS on Fundamentals, vol. E80-A, no. 12, pp. 2562-2571, December 1997, doi: .
Abstract: Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e80-a_12_2562/_p

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@ARTICLE{e80-a_12_2562,
author={Nobuhiko SUGINO, Hironobu MIYAZAKI, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses},
year={1997},
volume={E80-A},
number={12},
pages={2562-2571},
abstract={Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2562
EP - 2571
AU - Nobuhiko SUGINO
AU - Hironobu MIYAZAKI
AU - Akinori NISHIHARA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1997
AB - Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.
ER -