An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator

Akira YASUDA; Hiroshi TANIMOTO; Chikau TAKAHASHI; Akira YAMAGUCHI; Masayuki KOIZUMI

An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator

Akira YASUDA, Hiroshi TANIMOTO, Chikau TAKAHASHI, Akira YAMAGUCHI, Masayuki KOIZUMI

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A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.2 pp.291-295

Publication Date: 1997/02/25

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Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)

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Akira YASUDA, Hiroshi TANIMOTO, Chikau TAKAHASHI, Akira YAMAGUCHI, Masayuki KOIZUMI, "An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator" in IEICE TRANSACTIONS on Fundamentals, vol. E80-A, no. 2, pp. 291-295, February 1997, doi: .
Abstract: A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e80-a_2_291/_p

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@ARTICLE{e80-a_2_291,
author={Akira YASUDA, Hiroshi TANIMOTO, Chikau TAKAHASHI, Akira YAMAGUCHI, Masayuki KOIZUMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator},
year={1997},
volume={E80-A},
number={2},
pages={291-295},
abstract={A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 291
EP - 295
AU - Akira YASUDA
AU - Hiroshi TANIMOTO
AU - Chikau TAKAHASHI
AU - Akira YAMAGUCHI
AU - Masayuki KOIZUMI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1997
AB - A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.
ER -