Register-Transfer Level Testability Analysis and Its Application to Design for Testability

Mizuki TAKAHASHI; Ryoji SAKURAI; Hiroaki NODA; Takashi KAMBE

Register-Transfer Level Testability Analysis and Its Application to Design for Testability

Mizuki TAKAHASHI, Ryoji SAKURAI, Hiroaki NODA, Takashi KAMBE

Full Text Views

0

Share
Cite this

Summary :

In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.12 pp.2646-2654

Publication Date: 1998/12/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Test

Cite this

Copy

Mizuki TAKAHASHI, Ryoji SAKURAI, Hiroaki NODA, Takashi KAMBE, "Register-Transfer Level Testability Analysis and Its Application to Design for Testability" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 12, pp. 2646-2654, December 1998, doi: .
Abstract: In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2646/_p

Copy

@ARTICLE{e81-a_12_2646,
author={Mizuki TAKAHASHI, Ryoji SAKURAI, Hiroaki NODA, Takashi KAMBE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Register-Transfer Level Testability Analysis and Its Application to Design for Testability},
year={1998},
volume={E81-A},
number={12},
pages={2646-2654},
abstract={In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - Register-Transfer Level Testability Analysis and Its Application to Design for Testability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2646
EP - 2654
AU - Mizuki TAKAHASHI
AU - Ryoji SAKURAI
AU - Hiroaki NODA
AU - Takashi KAMBE
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.
ER -