An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology

Takumi WATANABE; Yusuke OHTOMO; Kimihiro YAMAKOSHI; Yuichiro TAKEI

An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology

Takumi WATANABE, Yusuke OHTOMO, Kimihiro YAMAKOSHI, Yuichiro TAKEI

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This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.4 pp.677-684

Publication Date: 1998/04/25

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Category: VLSI Design Technology and CAD

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Takumi WATANABE, Yusuke OHTOMO, Kimihiro YAMAKOSHI, Yuichiro TAKEI, "An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 4, pp. 677-684, April 1998, doi: .
Abstract: This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_4_677/_p

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@ARTICLE{e81-a_4_677,
author={Takumi WATANABE, Yusuke OHTOMO, Kimihiro YAMAKOSHI, Yuichiro TAKEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology},
year={1998},
volume={E81-A},
number={4},
pages={677-684},
abstract={This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 677
EP - 684
AU - Takumi WATANABE
AU - Yusuke OHTOMO
AU - Kimihiro YAMAKOSHI
AU - Yuichiro TAKEI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 1998
AB - This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.
ER -