FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model

Kei EGUCHI; Takahiro INOUE; Akio TSUNEDA

FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model

Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA

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In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.6 pp.1176-1178

Publication Date: 1998/06/25

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Type of Manuscript: Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)

Category: Nonlinear Problems

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Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, "FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 6, pp. 1176-1178, June 1998, doi: .
Abstract: In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_6_1176/_p

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@ARTICLE{e81-a_6_1176,
author={Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model},
year={1998},
volume={E81-A},
number={6},
pages={1176-1178},
abstract={In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1176
EP - 1178
AU - Kei EGUCHI
AU - Takahiro INOUE
AU - Akio TSUNEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1998
AB - In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.
ER -