Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm

Li JIANG; Dongju LI; Shintaro HABA; Chawalit HONSAWEK; Hiroaki KUNIEDA

Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm

Li JIANG, Dongju LI, Shintaro HABA, Chawalit HONSAWEK, Hiroaki KUNIEDA

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In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.8 pp.1667-1675

Publication Date: 1998/08/25

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Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)

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Li JIANG, Dongju LI, Shintaro HABA, Chawalit HONSAWEK, Hiroaki KUNIEDA, "Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 8, pp. 1667-1675, August 1998, doi: .
Abstract: In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_8_1667/_p

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@ARTICLE{e81-a_8_1667,
author={Li JIANG, Dongju LI, Shintaro HABA, Chawalit HONSAWEK, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm},
year={1998},
volume={E81-A},
number={8},
pages={1667-1675},
abstract={In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1667
EP - 1675
AU - Li JIANG
AU - Dongju LI
AU - Shintaro HABA
AU - Chawalit HONSAWEK
AU - Hiroaki KUNIEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1998
AB - In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.
ER -