Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks

Satoshi KOMATSU; Masahiro FUJITA

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks

Satoshi KOMATSU, Masahiro FUJITA

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The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3001-3008

Publication Date: 2003/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Power Optimization

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Satoshi KOMATSU, Masahiro FUJITA, "Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3001-3008, December 2003, doi: .
Abstract: The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3001/_p

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@ARTICLE{e86-a_12_3001,
author={Satoshi KOMATSU, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks},
year={2003},
volume={E86-A},
number={12},
pages={3001-3008},
abstract={The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3001
EP - 3008
AU - Satoshi KOMATSU
AU - Masahiro FUJITA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.
ER -