Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

Jing-Jia LIOU; Li-C. WANG; Angela KRSTIĆ; Kwang-Ting (Tim) CHENG

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

Jing-Jia LIOU, Li-C. WANG, Angela KRSTIĆ, Kwang-Ting (Tim) CHENG

Full Text Views

0

Share
Cite this

Summary :

Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3038-3048

Publication Date: 2003/12/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Timing Verification and Test Generation

Cite this

Copy

Jing-Jia LIOU, Li-C. WANG, Angela KRSTIĆ, Kwang-Ting (Tim) CHENG, "Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3038-3048, December 2003, doi: .
Abstract: Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3038/_p

Copy

@ARTICLE{e86-a_12_3038,
author={Jing-Jia LIOU, Li-C. WANG, Angela KRSTIĆ, Kwang-Ting (Tim) CHENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation},
year={2003},
volume={E86-A},
number={12},
pages={3038-3048},
abstract={Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3038
EP - 3048
AU - Jing-Jia LIOU
AU - Li-C. WANG
AU - Angela KRSTIĆ
AU - Kwang-Ting (Tim) CHENG
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.
ER -