A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Nozomu TOGAWA; Kyosuke KASAHARA; Yuichiro MIYAOKA; Jinku CHOI; Masao YANAGISAWA; Tatsuo OHTSUKI

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Nozomu TOGAWA, Kyosuke KASAHARA, Yuichiro MIYAOKA, Jinku CHOI, Masao YANAGISAWA, Tatsuo OHTSUKI

Full Text Views

0

Share
Cite this

Summary :

A packed SIMD type operation or a SIMD operation is n-parallel b/n-bit sub-operations executed by the modified n-bit functional unit. Such a functional unit is called a SIMD functional unit and a processor core which can execute SIMD operations is called a SIMD processor core. SIMD operations can be effectively applied to image processing applications. This paper focuses on hardware/software cosynthesis of SIMD processor cores and particularly proposes a new simulator generator which simulates pipelined instructions for a SIMD processor. Generally, a SIMD functional unit has many options and then we can have so many different SIMD functional unit instances. However, since our hardware/software cosynthesis system synthesizes a special-purpose processor core for an input application program, it uses very limited SIMD functional unit instances. In the proposed approach, we consider a SIMD operation to be a set of SIMD sub-operations. By adding up the appropriate SIMD sub-operations, we construct a single SIMD operation. Then a SIMD functional unit behavior can be characterized by a collection of SIMD operations. This approach has the advantage that: if we have a small number of behavior libraries for SIMD sub-operations, we can instantiate a particular SIMD functional unit behavior. Experimental results demonstrate the effectiveness of the proposed approach.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3099-3109

Publication Date: 2003/12/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Simulation Accelerator

Cite this

Copy

Nozomu TOGAWA, Kyosuke KASAHARA, Yuichiro MIYAOKA, Jinku CHOI, Masao YANAGISAWA, Tatsuo OHTSUKI, "A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3099-3109, December 2003, doi: .
Abstract: A packed SIMD type operation or a SIMD operation is n-parallel b/n-bit sub-operations executed by the modified n-bit functional unit. Such a functional unit is called a SIMD functional unit and a processor core which can execute SIMD operations is called a SIMD processor core. SIMD operations can be effectively applied to image processing applications. This paper focuses on hardware/software cosynthesis of SIMD processor cores and particularly proposes a new simulator generator which simulates pipelined instructions for a SIMD processor. Generally, a SIMD functional unit has many options and then we can have so many different SIMD functional unit instances. However, since our hardware/software cosynthesis system synthesizes a special-purpose processor core for an input application program, it uses very limited SIMD functional unit instances. In the proposed approach, we consider a SIMD operation to be a set of SIMD sub-operations. By adding up the appropriate SIMD sub-operations, we construct a single SIMD operation. Then a SIMD functional unit behavior can be characterized by a collection of SIMD operations. This approach has the advantage that: if we have a small number of behavior libraries for SIMD sub-operations, we can instantiate a particular SIMD functional unit behavior. Experimental results demonstrate the effectiveness of the proposed approach.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3099/_p

Copy

@ARTICLE{e86-a_12_3099,
author={Nozomu TOGAWA, Kyosuke KASAHARA, Yuichiro MIYAOKA, Jinku CHOI, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions},
year={2003},
volume={E86-A},
number={12},
pages={3099-3109},
abstract={A packed SIMD type operation or a SIMD operation is n-parallel b/n-bit sub-operations executed by the modified n-bit functional unit. Such a functional unit is called a SIMD functional unit and a processor core which can execute SIMD operations is called a SIMD processor core. SIMD operations can be effectively applied to image processing applications. This paper focuses on hardware/software cosynthesis of SIMD processor cores and particularly proposes a new simulator generator which simulates pipelined instructions for a SIMD processor. Generally, a SIMD functional unit has many options and then we can have so many different SIMD functional unit instances. However, since our hardware/software cosynthesis system synthesizes a special-purpose processor core for an input application program, it uses very limited SIMD functional unit instances. In the proposed approach, we consider a SIMD operation to be a set of SIMD sub-operations. By adding up the appropriate SIMD sub-operations, we construct a single SIMD operation. Then a SIMD functional unit behavior can be characterized by a collection of SIMD operations. This approach has the advantage that: if we have a small number of behavior libraries for SIMD sub-operations, we can instantiate a particular SIMD functional unit behavior. Experimental results demonstrate the effectiveness of the proposed approach.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3099
EP - 3109
AU - Nozomu TOGAWA
AU - Kyosuke KASAHARA
AU - Yuichiro MIYAOKA
AU - Jinku CHOI
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - A packed SIMD type operation or a SIMD operation is n-parallel b/n-bit sub-operations executed by the modified n-bit functional unit. Such a functional unit is called a SIMD functional unit and a processor core which can execute SIMD operations is called a SIMD processor core. SIMD operations can be effectively applied to image processing applications. This paper focuses on hardware/software cosynthesis of SIMD processor cores and particularly proposes a new simulator generator which simulates pipelined instructions for a SIMD processor. Generally, a SIMD functional unit has many options and then we can have so many different SIMD functional unit instances. However, since our hardware/software cosynthesis system synthesizes a special-purpose processor core for an input application program, it uses very limited SIMD functional unit instances. In the proposed approach, we consider a SIMD operation to be a set of SIMD sub-operations. By adding up the appropriate SIMD sub-operations, we construct a single SIMD operation. Then a SIMD functional unit behavior can be characterized by a collection of SIMD operations. This approach has the advantage that: if we have a small number of behavior libraries for SIMD sub-operations, we can instantiate a particular SIMD functional unit behavior. Experimental results demonstrate the effectiveness of the proposed approach.
ER -