Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder

Chung-Jr LIAN; Zhong-Lan YANG; Hao-Chieh CHANG; Liang-Gee CHEN

Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder

Chung-Jr LIAN, Zhong-Lan YANG, Hao-Chieh CHANG, Liang-Gee CHEN

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This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.2 pp.472-479

Publication Date: 2003/02/01

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Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Chung-Jr LIAN, Zhong-Lan YANG, Hao-Chieh CHANG, Liang-Gee CHEN, "Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 2, pp. 472-479, February 2003, doi: .
Abstract: This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_2_472/_p

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@ARTICLE{e86-a_2_472,
author={Chung-Jr LIAN, Zhong-Lan YANG, Hao-Chieh CHANG, Liang-Gee CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder},
year={2003},
volume={E86-A},
number={2},
pages={472-479},
abstract={This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 472
EP - 479
AU - Chung-Jr LIAN
AU - Zhong-Lan YANG
AU - Hao-Chieh CHANG
AU - Liang-Gee CHEN
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2003
AB - This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.
ER -