Pre-Route Power Analysis Techniques for SoC

Takashi YAMADA; Takeshi SAKAMOTO; Shinji FURUICHI; Mamoru MUKUNO; Yoshifumi MATSUSHITA; Hiroto YASUURA

Pre-Route Power Analysis Techniques for SoC

Takashi YAMADA, Takeshi SAKAMOTO, Shinji FURUICHI, Mamoru MUKUNO, Yoshifumi MATSUSHITA, Hiroto YASUURA

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This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.3 pp.686-692

Publication Date: 2003/03/01

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Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Takashi YAMADA, Takeshi SAKAMOTO, Shinji FURUICHI, Mamoru MUKUNO, Yoshifumi MATSUSHITA, Hiroto YASUURA, "Pre-Route Power Analysis Techniques for SoC" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 3, pp. 686-692, March 2003, doi: .
Abstract: This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_3_686/_p

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@ARTICLE{e86-a_3_686,
author={Takashi YAMADA, Takeshi SAKAMOTO, Shinji FURUICHI, Mamoru MUKUNO, Yoshifumi MATSUSHITA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Pre-Route Power Analysis Techniques for SoC},
year={2003},
volume={E86-A},
number={3},
pages={686-692},
abstract={This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Pre-Route Power Analysis Techniques for SoC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 686
EP - 692
AU - Takashi YAMADA
AU - Takeshi SAKAMOTO
AU - Shinji FURUICHI
AU - Mamoru MUKUNO
AU - Yoshifumi MATSUSHITA
AU - Hiroto YASUURA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2003
AB - This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.
ER -