A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Nozomu TOGAWA; Takao TOTSUKA; Tatsuhiko WAKUI; Masao YANAGISAWA; Tatsuo OHTSUKI

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Nozomu TOGAWA, Takao TOTSUKA, Tatsuhiko WAKUI, Masao YANAGISAWA, Tatsuo OHTSUKI

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Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.5 pp.1082-1092

Publication Date: 2003/05/01

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Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)

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Nozomu TOGAWA, Takao TOTSUKA, Tatsuhiko WAKUI, Masao YANAGISAWA, Tatsuo OHTSUKI, "A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 5, pp. 1082-1092, May 2003, doi: .
Abstract: Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_5_1082/_p

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@ARTICLE{e86-a_5_1082,
author={Nozomu TOGAWA, Takao TOTSUKA, Tatsuhiko WAKUI, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories},
year={2003},
volume={E86-A},
number={5},
pages={1082-1092},
abstract={Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1082
EP - 1092
AU - Nozomu TOGAWA
AU - Takao TOTSUKA
AU - Tatsuhiko WAKUI
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2003
AB - Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.
ER -