Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints

Makoto SUGIHARA; Kazuaki MURAKAMI; Yusuke MATSUNAGA

Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints

Makoto SUGIHARA, Kazuaki MURAKAMI, Yusuke MATSUNAGA

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In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3174-3184

Publication Date: 2004/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Test

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Makoto SUGIHARA, Kazuaki MURAKAMI, Yusuke MATSUNAGA, "Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 12, pp. 3174-3184, December 2004, doi: .
Abstract: In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3174/_p

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@ARTICLE{e87-a_12_3174,
author={Makoto SUGIHARA, Kazuaki MURAKAMI, Yusuke MATSUNAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints},
year={2004},
volume={E87-A},
number={12},
pages={3174-3184},
abstract={In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3174
EP - 3184
AU - Makoto SUGIHARA
AU - Kazuaki MURAKAMI
AU - Yusuke MATSUNAGA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.
ER -