A Design Scheme for Delay Testing of Controllers Using State Transition Information

Tsuyoshi IWAGAKI; Satoshi OHTAKE; Hideo FUJIWARA

A Design Scheme for Delay Testing of Controllers Using State Transition Information

Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA

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This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3200-3207

Publication Date: 2004/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Test

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Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA, "A Design Scheme for Delay Testing of Controllers Using State Transition Information" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 12, pp. 3200-3207, December 2004, doi: .
Abstract: This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3200/_p

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@ARTICLE{e87-a_12_3200,
author={Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design Scheme for Delay Testing of Controllers Using State Transition Information},
year={2004},
volume={E87-A},
number={12},
pages={3200-3207},
abstract={This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Design Scheme for Delay Testing of Controllers Using State Transition Information
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3200
EP - 3207
AU - Tsuyoshi IWAGAKI
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.
ER -