A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

Koki IGAWA; Masao YANAGISAWA; Nozomu TOGAWA

doi:10.1587/transfun.E100.A.1439

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

Koki IGAWA, Masao YANAGISAWA, Nozomu TOGAWA

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In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.7 pp.1439-1451

Publication Date: 2017/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.1439

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Koki IGAWA
  Waseda University
Masao YANAGISAWA
  Waseda University
Nozomu TOGAWA
  Waseda University

Keyword

high-level synthesis, delay variation, body biasing, interconnection delay, floorplan

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Koki IGAWA, Masao YANAGISAWA, Nozomu TOGAWA, "A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 7, pp. 1439-1451, July 2017, doi: 10.1587/transfun.E100.A.1439.
Abstract: In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.1439/_p

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@ARTICLE{e100-a_7_1439,
author={Koki IGAWA, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation},
year={2017},
volume={E100-A},
number={7},
pages={1439-1451},
abstract={In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.},
keywords={},
doi={10.1587/transfun.E100.A.1439},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1439
EP - 1451
AU - Koki IGAWA
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2017
DO - 10.1587/transfun.E100.A.1439
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2017
AB - In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.
ER -