Worst-Case Performance of ILIFC with Inversion Cells

Akira YAMAWAKI; Hiroshi KAMABE; Shan LU

doi:10.1587/transfun.E100.A.2662

Worst-Case Performance of ILIFC with Inversion Cells

Akira YAMAWAKI, Hiroshi KAMABE, Shan LU

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Index-less Indexed Flash Code (ILIFC) is a coding scheme for flash memories in which one bit of a data sequence is stored in a slice consisting of several cells but the index of the bit is stored implicitly. Although several modified ILIFC schemes have been proposed, in this research we consider an ILIFC with inversion cells (I-ILIFC). The I-ILIFC reduces the total number of cell level changes at each write request. Computer simulation is used to show that the I-ILIFC improves the average performance of the ILIFC in many cases. This paper presents our derivation of the lower bound on the number of write operations by I-ILIFC and shows that the worst-case performance of the I-ILIFC is better than that of the ILIFC if the code length is sufficiently large. Additionally, we consider another lower bound thereon. The results show that the threshold of the code length that determines whether the I-ILIFC improves the worst-case performance of the ILIFC is lower than that in the first lower bound.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2662-2670

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2662

Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications)

Category: Coding Theory for Strage

Authors

Akira YAMAWAKI
  Gifu University
Hiroshi KAMABE
  Gifu University
Shan LU
  Gifu University

Keyword

flash memory, block erasure, index-less indexed flash code

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Akira YAMAWAKI, Hiroshi KAMABE, Shan LU, "Worst-Case Performance of ILIFC with Inversion Cells" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2662-2670, December 2017, doi: 10.1587/transfun.E100.A.2662.
Abstract: Index-less Indexed Flash Code (ILIFC) is a coding scheme for flash memories in which one bit of a data sequence is stored in a slice consisting of several cells but the index of the bit is stored implicitly. Although several modified ILIFC schemes have been proposed, in this research we consider an ILIFC with inversion cells (I-ILIFC). The I-ILIFC reduces the total number of cell level changes at each write request. Computer simulation is used to show that the I-ILIFC improves the average performance of the ILIFC in many cases. This paper presents our derivation of the lower bound on the number of write operations by I-ILIFC and shows that the worst-case performance of the I-ILIFC is better than that of the ILIFC if the code length is sufficiently large. Additionally, we consider another lower bound thereon. The results show that the threshold of the code length that determines whether the I-ILIFC improves the worst-case performance of the ILIFC is lower than that in the first lower bound.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2662/_p

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@ARTICLE{e100-a_12_2662,
author={Akira YAMAWAKI, Hiroshi KAMABE, Shan LU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Worst-Case Performance of ILIFC with Inversion Cells},
year={2017},
volume={E100-A},
number={12},
pages={2662-2670},
abstract={Index-less Indexed Flash Code (ILIFC) is a coding scheme for flash memories in which one bit of a data sequence is stored in a slice consisting of several cells but the index of the bit is stored implicitly. Although several modified ILIFC schemes have been proposed, in this research we consider an ILIFC with inversion cells (I-ILIFC). The I-ILIFC reduces the total number of cell level changes at each write request. Computer simulation is used to show that the I-ILIFC improves the average performance of the ILIFC in many cases. This paper presents our derivation of the lower bound on the number of write operations by I-ILIFC and shows that the worst-case performance of the I-ILIFC is better than that of the ILIFC if the code length is sufficiently large. Additionally, we consider another lower bound thereon. The results show that the threshold of the code length that determines whether the I-ILIFC improves the worst-case performance of the ILIFC is lower than that in the first lower bound.},
keywords={},
doi={10.1587/transfun.E100.A.2662},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Worst-Case Performance of ILIFC with Inversion Cells
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2662
EP - 2670
AU - Akira YAMAWAKI
AU - Hiroshi KAMABE
AU - Shan LU
PY - 2017
DO - 10.1587/transfun.E100.A.2662
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - Index-less Indexed Flash Code (ILIFC) is a coding scheme for flash memories in which one bit of a data sequence is stored in a slice consisting of several cells but the index of the bit is stored implicitly. Although several modified ILIFC schemes have been proposed, in this research we consider an ILIFC with inversion cells (I-ILIFC). The I-ILIFC reduces the total number of cell level changes at each write request. Computer simulation is used to show that the I-ILIFC improves the average performance of the ILIFC in many cases. This paper presents our derivation of the lower bound on the number of write operations by I-ILIFC and shows that the worst-case performance of the I-ILIFC is better than that of the ILIFC if the code length is sufficiently large. Additionally, we consider another lower bound thereon. The results show that the threshold of the code length that determines whether the I-ILIFC improves the worst-case performance of the ILIFC is lower than that in the first lower bound.
ER -