A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems

Seiji MOCHIZUKI; Katsushige MATSUBARA; Keisuke MATSUMOTO; Chi Lan Phuong NGUYEN; Tetsuya SHIBAYAMA; Kenichi IWATA; Katsuya MIZUMOTO; Takahiro IRITA; Hirotaka HARA; Toshihiro HATTORI

doi:10.1587/transfun.E100.A.2878

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems

Seiji MOCHIZUKI, Katsushige MATSUBARA, Keisuke MATSUMOTO, Chi Lan Phuong NGUYEN, Tetsuya SHIBAYAMA, Kenichi IWATA, Katsuya MIZUMOTO, Takahiro IRITA, Hirotaka HARA, Toshihiro HATTORI

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A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2878-2887

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2878

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Authors

Seiji MOCHIZUKI
  Renesas Electronics Corporation
Katsushige MATSUBARA
  Renesas Electronics Corporation
Keisuke MATSUMOTO
  Renesas Electronics Corporation
Chi Lan Phuong NGUYEN
  Renesas Design Vietnam
Tetsuya SHIBAYAMA
  Renesas Electronics Corporation
Kenichi IWATA
  Renesas Electronics Corporation
Katsuya MIZUMOTO
  Renesas Electronics Corporation
Takahiro IRITA
  Renesas Design Vietnam
Hirotaka HARA
  Renesas Design Vietnam
Toshihiro HATTORI
  Renesas Electronics Corporation

Keyword

video processing, automotive, low latency, memory-access-data compression

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Seiji MOCHIZUKI, Katsushige MATSUBARA, Keisuke MATSUMOTO, Chi Lan Phuong NGUYEN, Tetsuya SHIBAYAMA, Kenichi IWATA, Katsuya MIZUMOTO, Takahiro IRITA, Hirotaka HARA, Toshihiro HATTORI, "A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2878-2887, December 2017, doi: 10.1587/transfun.E100.A.2878.
Abstract: A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2878/_p

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@ARTICLE{e100-a_12_2878,
author={Seiji MOCHIZUKI, Katsushige MATSUBARA, Keisuke MATSUMOTO, Chi Lan Phuong NGUYEN, Tetsuya SHIBAYAMA, Kenichi IWATA, Katsuya MIZUMOTO, Takahiro IRITA, Hirotaka HARA, Toshihiro HATTORI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems},
year={2017},
volume={E100-A},
number={12},
pages={2878-2887},
abstract={A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.},
keywords={},
doi={10.1587/transfun.E100.A.2878},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2878
EP - 2887
AU - Seiji MOCHIZUKI
AU - Katsushige MATSUBARA
AU - Keisuke MATSUMOTO
AU - Chi Lan Phuong NGUYEN
AU - Tetsuya SHIBAYAMA
AU - Kenichi IWATA
AU - Katsuya MIZUMOTO
AU - Takahiro IRITA
AU - Hirotaka HARA
AU - Toshihiro HATTORI
PY - 2017
DO - 10.1587/transfun.E100.A.2878
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.
ER -