A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems

Kai-Feng XIA; Bin WU; Tao XIONG; Tian-Chun YE; Cheng-Ying CHEN

doi:10.1587/transfun.E100.A.592

A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems

Kai-Feng XIA, Bin WU, Tao XIONG, Tian-Chun YE, Cheng-Ying CHEN

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In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm² core area with 82.6mW power consumption at 122.88MHz clock frequency.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.2 pp.592-601

Publication Date: 2017/02/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.592

Type of Manuscript: PAPER

Category: Digital Signal Processing

Authors

Kai-Feng XIA
  the Institute of Microelectronics of Chinese Academy of Sciences
Bin WU
  the Institute of Microelectronics of Chinese Academy of Sciences
Tao XIONG
  the Institute of Microelectronics of Chinese Academy of Sciences
Tian-Chun YE
  the Institute of Microelectronics of Chinese Academy of Sciences
Cheng-Ying CHEN
  the Institute of Microelectronics of Chinese Academy of Sciences

Keyword

multiple-input and multiple-output (MIMO), pipeline FFT processor, multipath delay feedback (MDF), multipath delay commutator (MDC), bit-reversal circuits, long term evolution (LTE)

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Kai-Feng XIA, Bin WU, Tao XIONG, Tian-Chun YE, Cheng-Ying CHEN, "A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 2, pp. 592-601, February 2017, doi: 10.1587/transfun.E100.A.592.
Abstract: In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm² core area with 82.6mW power consumption at 122.88MHz clock frequency.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.592/_p

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@ARTICLE{e100-a_2_592,
author={Kai-Feng XIA, Bin WU, Tao XIONG, Tian-Chun YE, Cheng-Ying CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems},
year={2017},
volume={E100-A},
number={2},
pages={592-601},
abstract={In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm² core area with 82.6mW power consumption at 122.88MHz clock frequency.},
keywords={},
doi={10.1587/transfun.E100.A.592},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 592
EP - 601
AU - Kai-Feng XIA
AU - Bin WU
AU - Tao XIONG
AU - Tian-Chun YE
AU - Cheng-Ying CHEN
PY - 2017
DO - 10.1587/transfun.E100.A.592
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2017
AB - In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm² core area with 82.6mW power consumption at 122.88MHz clock frequency.
ER -