C Description Reconstruction Method from a Revised Netlist for ECO Support

Yusuke KIMURA; Amir Masoud GHAREHBAGHI; Masahiro FUJITA

doi:10.1587/transfun.E101.A.685

C Description Reconstruction Method from a Revised Netlist for ECO Support

Yusuke KIMURA, Amir Masoud GHAREHBAGHI, Masahiro FUJITA

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In the process of VLSI design, ECO (Engineering Change Order) may occur at any design phase. When ECO happens after the netlist is generated and optimized, designers may like to modify the netlist directly. This is because if ECO is performed in the high-level description, the netlist should be resynthesized and the result may be significantly different from the original one, even if the modification in the high-level description is small. As the result, the efforts spent on optimization so far may become useless. When the netlist is modified directly, the C description should be revised accordingly. This paper proposes a method to reconstruct a C description from the revised netlist. In the proposed method, designers need to provide a template represented in C, which has some vacant (blanked) places and is created from the original C description. The vacant places are automatically synthesized using a CEGIS-based method (Counter Example Guided Inductive Synthesis). Using a set of use-cases, our method tries to find the correct expressions for the vacant places so that the entire description becomes functionally equivalent to the given modified netlist, by only simulating the netlist. Experimental results show that the proposed method can reconstruct C descriptions successfully within practical time for several examples including the one having around 9,000 lines of executable statements. Moreover, the proposed method can be applied to equivalence checking between a netlist and a C description, as shown by our experimental results.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.4 pp.685-696

Publication Date: 2018/04/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E101.A.685

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

Authors

Yusuke KIMURA
  The University of Tokyo
Amir Masoud GHAREHBAGHI
  The University of Tokyo
Masahiro FUJITA
  The University of Tokyo

Keyword

C reconstruction, ECO, CEGIS, program synthesis

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Yusuke KIMURA, Amir Masoud GHAREHBAGHI, Masahiro FUJITA, "C Description Reconstruction Method from a Revised Netlist for ECO Support" in IEICE TRANSACTIONS on Fundamentals, vol. E101-A, no. 4, pp. 685-696, April 2018, doi: 10.1587/transfun.E101.A.685.
Abstract: In the process of VLSI design, ECO (Engineering Change Order) may occur at any design phase. When ECO happens after the netlist is generated and optimized, designers may like to modify the netlist directly. This is because if ECO is performed in the high-level description, the netlist should be resynthesized and the result may be significantly different from the original one, even if the modification in the high-level description is small. As the result, the efforts spent on optimization so far may become useless. When the netlist is modified directly, the C description should be revised accordingly. This paper proposes a method to reconstruct a C description from the revised netlist. In the proposed method, designers need to provide a template represented in C, which has some vacant (blanked) places and is created from the original C description. The vacant places are automatically synthesized using a CEGIS-based method (Counter Example Guided Inductive Synthesis). Using a set of use-cases, our method tries to find the correct expressions for the vacant places so that the entire description becomes functionally equivalent to the given modified netlist, by only simulating the netlist. Experimental results show that the proposed method can reconstruct C descriptions successfully within practical time for several examples including the one having around 9,000 lines of executable statements. Moreover, the proposed method can be applied to equivalence checking between a netlist and a C description, as shown by our experimental results.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.685/_p

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@ARTICLE{e101-a_4_685,
author={Yusuke KIMURA, Amir Masoud GHAREHBAGHI, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={C Description Reconstruction Method from a Revised Netlist for ECO Support},
year={2018},
volume={E101-A},
number={4},
pages={685-696},
abstract={In the process of VLSI design, ECO (Engineering Change Order) may occur at any design phase. When ECO happens after the netlist is generated and optimized, designers may like to modify the netlist directly. This is because if ECO is performed in the high-level description, the netlist should be resynthesized and the result may be significantly different from the original one, even if the modification in the high-level description is small. As the result, the efforts spent on optimization so far may become useless. When the netlist is modified directly, the C description should be revised accordingly. This paper proposes a method to reconstruct a C description from the revised netlist. In the proposed method, designers need to provide a template represented in C, which has some vacant (blanked) places and is created from the original C description. The vacant places are automatically synthesized using a CEGIS-based method (Counter Example Guided Inductive Synthesis). Using a set of use-cases, our method tries to find the correct expressions for the vacant places so that the entire description becomes functionally equivalent to the given modified netlist, by only simulating the netlist. Experimental results show that the proposed method can reconstruct C descriptions successfully within practical time for several examples including the one having around 9,000 lines of executable statements. Moreover, the proposed method can be applied to equivalence checking between a netlist and a C description, as shown by our experimental results.},
keywords={},
doi={10.1587/transfun.E101.A.685},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - C Description Reconstruction Method from a Revised Netlist for ECO Support
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 685
EP - 696
AU - Yusuke KIMURA
AU - Amir Masoud GHAREHBAGHI
AU - Masahiro FUJITA
PY - 2018
DO - 10.1587/transfun.E101.A.685
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2018
AB - In the process of VLSI design, ECO (Engineering Change Order) may occur at any design phase. When ECO happens after the netlist is generated and optimized, designers may like to modify the netlist directly. This is because if ECO is performed in the high-level description, the netlist should be resynthesized and the result may be significantly different from the original one, even if the modification in the high-level description is small. As the result, the efforts spent on optimization so far may become useless. When the netlist is modified directly, the C description should be revised accordingly. This paper proposes a method to reconstruct a C description from the revised netlist. In the proposed method, designers need to provide a template represented in C, which has some vacant (blanked) places and is created from the original C description. The vacant places are automatically synthesized using a CEGIS-based method (Counter Example Guided Inductive Synthesis). Using a set of use-cases, our method tries to find the correct expressions for the vacant places so that the entire description becomes functionally equivalent to the given modified netlist, by only simulating the netlist. Experimental results show that the proposed method can reconstruct C descriptions successfully within practical time for several examples including the one having around 9,000 lines of executable statements. Moreover, the proposed method can be applied to equivalence checking between a netlist and a C description, as shown by our experimental results.
ER -