Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher

Dai YAMAMOTO; Kouichi ITOH; Jun YAJIMA

doi:10.1587/transfun.E94.A.2628

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher

Dai YAMAMOTO, Kouichi ITOH, Jun YAJIMA

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Compact design is very important for embedded systems such as wireless sensor nodes, RFID tags and mobile devices because of their limited hardware (H/W) resources. This paper proposes a compact H/W implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [8] and [9], Yamamoto et al. proposed a method of reducing the register size for the MISTY1 FO function (YYI-08), and implemented very compact MISTY1 H/W. In this paper we aim to implement the smallest KASUMI H/W to date by applying a YYI-08 configuration to KASUMI, whose FO function has a similar structure to that of MISTY1. However, we discovered that straightforward application of YYI-08 raises problems. We therefore propose a new YYI-08 configuration improved for KASUMI and the compact H/W architecture. The new YYI-08 configuration consists of new FL function calculation schemes and a suitable calculation order. According to our logic synthesis on a 0.11-µm ASIC process, the gate size is 2.99 K gates, which, to our knowledge, is the smallest to date.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2628-2638

Publication Date: 2011/12/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E94.A.2628

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

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Dai YAMAMOTO, Kouichi ITOH, Jun YAJIMA, "Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher" in IEICE TRANSACTIONS on Fundamentals, vol. E94-A, no. 12, pp. 2628-2638, December 2011, doi: 10.1587/transfun.E94.A.2628.
Abstract: Compact design is very important for embedded systems such as wireless sensor nodes, RFID tags and mobile devices because of their limited hardware (H/W) resources. This paper proposes a compact H/W implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [8] and [9], Yamamoto et al. proposed a method of reducing the register size for the MISTY1 FO function (YYI-08), and implemented very compact MISTY1 H/W. In this paper we aim to implement the smallest KASUMI H/W to date by applying a YYI-08 configuration to KASUMI, whose FO function has a similar structure to that of MISTY1. However, we discovered that straightforward application of YYI-08 raises problems. We therefore propose a new YYI-08 configuration improved for KASUMI and the compact H/W architecture. The new YYI-08 configuration consists of new FL function calculation schemes and a suitable calculation order. According to our logic synthesis on a 0.11-µm ASIC process, the gate size is 2.99 K gates, which, to our knowledge, is the smallest to date.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2628/_p

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@ARTICLE{e94-a_12_2628,
author={Dai YAMAMOTO, Kouichi ITOH, Jun YAJIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher},
year={2011},
volume={E94-A},
number={12},
pages={2628-2638},
abstract={Compact design is very important for embedded systems such as wireless sensor nodes, RFID tags and mobile devices because of their limited hardware (H/W) resources. This paper proposes a compact H/W implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [8] and [9], Yamamoto et al. proposed a method of reducing the register size for the MISTY1 FO function (YYI-08), and implemented very compact MISTY1 H/W. In this paper we aim to implement the smallest KASUMI H/W to date by applying a YYI-08 configuration to KASUMI, whose FO function has a similar structure to that of MISTY1. However, we discovered that straightforward application of YYI-08 raises problems. We therefore propose a new YYI-08 configuration improved for KASUMI and the compact H/W architecture. The new YYI-08 configuration consists of new FL function calculation schemes and a suitable calculation order. According to our logic synthesis on a 0.11-µm ASIC process, the gate size is 2.99 K gates, which, to our knowledge, is the smallest to date.},
keywords={},
doi={10.1587/transfun.E94.A.2628},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2628
EP - 2638
AU - Dai YAMAMOTO
AU - Kouichi ITOH
AU - Jun YAJIMA
PY - 2011
DO - 10.1587/transfun.E94.A.2628
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - Compact design is very important for embedded systems such as wireless sensor nodes, RFID tags and mobile devices because of their limited hardware (H/W) resources. This paper proposes a compact H/W implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [8] and [9], Yamamoto et al. proposed a method of reducing the register size for the MISTY1 FO function (YYI-08), and implemented very compact MISTY1 H/W. In this paper we aim to implement the smallest KASUMI H/W to date by applying a YYI-08 configuration to KASUMI, whose FO function has a similar structure to that of MISTY1. However, we discovered that straightforward application of YYI-08 raises problems. We therefore propose a new YYI-08 configuration improved for KASUMI and the compact H/W architecture. The new YYI-08 configuration consists of new FL function calculation schemes and a suitable calculation order. According to our logic synthesis on a 0.11-µm ASIC process, the gate size is 2.99 K gates, which, to our knowledge, is the smallest to date.
ER -