Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System

Ryohei HORI; Taisuke UEOKA; Taku OTANI; Masaya YOSHIKAWA; Takeshi FUJINO

doi:10.1587/transfun.E95.A.2182

Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System

Ryohei HORI, Taisuke UEOKA, Taku OTANI, Masaya YOSHIKAWA, Takeshi FUJINO

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A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2182-2190

Publication Date: 2012/12/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E95.A.2182

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Physical Level Design

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Ryohei HORI, Taisuke UEOKA, Taku OTANI, Masaya YOSHIKAWA, Takeshi FUJINO, "Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System" in IEICE TRANSACTIONS on Fundamentals, vol. E95-A, no. 12, pp. 2182-2190, December 2012, doi: 10.1587/transfun.E95.A.2182.
Abstract: A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2182/_p

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@ARTICLE{e95-a_12_2182,
author={Ryohei HORI, Taisuke UEOKA, Taku OTANI, Masaya YOSHIKAWA, Takeshi FUJINO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System},
year={2012},
volume={E95-A},
number={12},
pages={2182-2190},
abstract={A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.},
keywords={},
doi={10.1587/transfun.E95.A.2182},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2182
EP - 2190
AU - Ryohei HORI
AU - Taisuke UEOKA
AU - Taku OTANI
AU - Masaya YOSHIKAWA
AU - Takeshi FUJINO
PY - 2012
DO - 10.1587/transfun.E95.A.2182
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.
ER -