Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}

Ming-Hwa SHEU; Yuan-Ching KUO; Su-Hon LIN; Siang-Min SIAO

doi:10.1587/transfun.E96.A.1571

Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2^{n + k}, 2ⁿ + 1, 2ⁿ - 1, 2²ⁿ + 1}

Ming-Hwa SHEU, Yuan-Ching KUO, Su-Hon LIN, Siang-Min SIAO

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This paper presents a novel adaptable 4-moduli set {2^{n + k}, 2ⁿ+1, 2ⁿ-1, 2²ⁿ+1}. It offers diverse dynamic ranges (DRs) from 2⁵ⁿ-2ⁿ to 2^{5n + k}-2^{n + k} that are used to conquer the over-range issue in RNS-application hardware designs. The proposed adaptable set possesses the coarse parameter n and fine parameter k. It not only has better parallelism and larger dynamic range (DR) than the existing adaptive 3-moduli sets, but also holds more sizable and flexible than the general 4-moduli sets with single parameter. For the adaptable R-to-B conversion, this paper first derives a fast reverse converting algorithm based on Chinese Remainder Theorem (CRT) and then presents the efficient converter architecture. From the experimental results, the proposed adaptable converter achieves better hardware performance in various DRs. Based on TSMC 0.18 µm CMOS technology, the proposed converter design is implemented and its results get at least 20.93% saving of Area-Delay-Power (ADP) products on average when comparing with the latest converter works.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.7 pp.1571-1578

Publication Date: 2013/07/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.1571

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Ming-Hwa SHEU, Yuan-Ching KUO, Su-Hon LIN, Siang-Min SIAO, "Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 7, pp. 1571-1578, July 2013, doi: 10.1587/transfun.E96.A.1571.
Abstract: This paper presents a novel adaptable 4-moduli set {2^{n + k}, 2ⁿ+1, 2ⁿ-1, 2²ⁿ+1}. It offers diverse dynamic ranges (DRs) from 2⁵ⁿ-2ⁿ to 2^{5n + k}-2^{n + k} that are used to conquer the over-range issue in RNS-application hardware designs. The proposed adaptable set possesses the coarse parameter n and fine parameter k. It not only has better parallelism and larger dynamic range (DR) than the existing adaptive 3-moduli sets, but also holds more sizable and flexible than the general 4-moduli sets with single parameter. For the adaptable R-to-B conversion, this paper first derives a fast reverse converting algorithm based on Chinese Remainder Theorem (CRT) and then presents the efficient converter architecture. From the experimental results, the proposed adaptable converter achieves better hardware performance in various DRs. Based on TSMC 0.18 µm CMOS technology, the proposed converter design is implemented and its results get at least 20.93% saving of Area-Delay-Power (ADP) products on average when comparing with the latest converter works.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.1571/_p

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@ARTICLE{e96-a_7_1571,
author={Ming-Hwa SHEU, Yuan-Ching KUO, Su-Hon LIN, Siang-Min SIAO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}},
year={2013},
volume={E96-A},
number={7},
pages={1571-1578},
abstract={This paper presents a novel adaptable 4-moduli set {2^{n + k}, 2ⁿ+1, 2ⁿ-1, 2²ⁿ+1}. It offers diverse dynamic ranges (DRs) from 2⁵ⁿ-2ⁿ to 2^{5n + k}-2^{n + k} that are used to conquer the over-range issue in RNS-application hardware designs. The proposed adaptable set possesses the coarse parameter n and fine parameter k. It not only has better parallelism and larger dynamic range (DR) than the existing adaptive 3-moduli sets, but also holds more sizable and flexible than the general 4-moduli sets with single parameter. For the adaptable R-to-B conversion, this paper first derives a fast reverse converting algorithm based on Chinese Remainder Theorem (CRT) and then presents the efficient converter architecture. From the experimental results, the proposed adaptable converter achieves better hardware performance in various DRs. Based on TSMC 0.18 µm CMOS technology, the proposed converter design is implemented and its results get at least 20.93% saving of Area-Delay-Power (ADP) products on average when comparing with the latest converter works.},
keywords={},
doi={10.1587/transfun.E96.A.1571},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1571
EP - 1578
AU - Ming-Hwa SHEU
AU - Yuan-Ching KUO
AU - Su-Hon LIN
AU - Siang-Min SIAO
PY - 2013
DO - 10.1587/transfun.E96.A.1571
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2013
AB - This paper presents a novel adaptable 4-moduli set {2^{n + k}, 2ⁿ+1, 2ⁿ-1, 2²ⁿ+1}. It offers diverse dynamic ranges (DRs) from 2⁵ⁿ-2ⁿ to 2^{5n + k}-2^{n + k} that are used to conquer the over-range issue in RNS-application hardware designs. The proposed adaptable set possesses the coarse parameter n and fine parameter k. It not only has better parallelism and larger dynamic range (DR) than the existing adaptive 3-moduli sets, but also holds more sizable and flexible than the general 4-moduli sets with single parameter. For the adaptable R-to-B conversion, this paper first derives a fast reverse converting algorithm based on Chinese Remainder Theorem (CRT) and then presents the efficient converter architecture. From the experimental results, the proposed adaptable converter achieves better hardware performance in various DRs. Based on TSMC 0.18 µm CMOS technology, the proposed converter design is implemented and its results get at least 20.93% saving of Area-Delay-Power (ADP) products on average when comparing with the latest converter works.
ER -