Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes

Yichao LU; Gang HE; Guifen TIAN; Satoshi GOTO

doi:10.1587/transfun.E96.A.2652

Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes

Yichao LU, Gang HE, Guifen TIAN, Satoshi GOTO

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Recently, non-binary low-density parity-check (NB-LDPC) codes starts to show their superiority in achieving significant coding gains when moderate codeword lengths are adopted. However, the overwhelming decoding complexity keeps NB-LDPC codes from being widely employed in modern communication devices. This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity. It achieves competitive error performance compared with conventional Min-max algorithm. Simulation result on a (255,174) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity NB-LDPC decoding algorithms. A partial-parallel NB-LDPC decoder architecture for cyclic NB-LDPC codes is also developed based on this algorithm. Optimization schemes are employed to cut off hard decision symbols in RAMs and also to store only part of the reliability messages. In addition, the variable node units are redesigned especially for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2652-2659

Publication Date: 2013/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.2652

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

Authors

Yichao LU
  Waseda University
Gang HE
  Waseda University
Guifen TIAN
  Waseda University
Satoshi GOTO
  Waseda University

Keyword

Belief propagation algorithm, iterative majority-logic decoding, low-density parity-check codes, non-binary, VLSI

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Yichao LU, Gang HE, Guifen TIAN, Satoshi GOTO, "Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 12, pp. 2652-2659, December 2013, doi: 10.1587/transfun.E96.A.2652.
Abstract: Recently, non-binary low-density parity-check (NB-LDPC) codes starts to show their superiority in achieving significant coding gains when moderate codeword lengths are adopted. However, the overwhelming decoding complexity keeps NB-LDPC codes from being widely employed in modern communication devices. This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity. It achieves competitive error performance compared with conventional Min-max algorithm. Simulation result on a (255,174) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity NB-LDPC decoding algorithms. A partial-parallel NB-LDPC decoder architecture for cyclic NB-LDPC codes is also developed based on this algorithm. Optimization schemes are employed to cut off hard decision symbols in RAMs and also to store only part of the reliability messages. In addition, the variable node units are redesigned especially for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2652/_p

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@ARTICLE{e96-a_12_2652,
author={Yichao LU, Gang HE, Guifen TIAN, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes},
year={2013},
volume={E96-A},
number={12},
pages={2652-2659},
abstract={Recently, non-binary low-density parity-check (NB-LDPC) codes starts to show their superiority in achieving significant coding gains when moderate codeword lengths are adopted. However, the overwhelming decoding complexity keeps NB-LDPC codes from being widely employed in modern communication devices. This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity. It achieves competitive error performance compared with conventional Min-max algorithm. Simulation result on a (255,174) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity NB-LDPC decoding algorithms. A partial-parallel NB-LDPC decoder architecture for cyclic NB-LDPC codes is also developed based on this algorithm. Optimization schemes are employed to cut off hard decision symbols in RAMs and also to store only part of the reliability messages. In addition, the variable node units are redesigned especially for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.},
keywords={},
doi={10.1587/transfun.E96.A.2652},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2652
EP - 2659
AU - Yichao LU
AU - Gang HE
AU - Guifen TIAN
AU - Satoshi GOTO
PY - 2013
DO - 10.1587/transfun.E96.A.2652
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - Recently, non-binary low-density parity-check (NB-LDPC) codes starts to show their superiority in achieving significant coding gains when moderate codeword lengths are adopted. However, the overwhelming decoding complexity keeps NB-LDPC codes from being widely employed in modern communication devices. This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity. It achieves competitive error performance compared with conventional Min-max algorithm. Simulation result on a (255,174) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity NB-LDPC decoding algorithms. A partial-parallel NB-LDPC decoder architecture for cyclic NB-LDPC codes is also developed based on this algorithm. Optimization schemes are employed to cut off hard decision symbols in RAMs and also to store only part of the reliability messages. In addition, the variable node units are redesigned especially for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.
ER -