A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility

Tiebin WU; Hengzhu LIU; Botao ZHANG

doi:10.1587/transfun.E97.A.1452

A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility

Tiebin WU, Hengzhu LIU, Botao ZHANG

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This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.7 pp.1452-1460

Publication Date: 2014/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E97.A.1452

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Tiebin WU
  National University of Defense Technology
Hengzhu LIU
  National University of Defense Technology
Botao ZHANG
  National University of Defense Technology

Keyword

test data compression, block merging, compatibility, test application time, code-based testing, system-on-chip (SoC)

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Tiebin WU, Hengzhu LIU, Botao ZHANG, "A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility" in IEICE TRANSACTIONS on Fundamentals, vol. E97-A, no. 7, pp. 1452-1460, July 2014, doi: 10.1587/transfun.E97.A.1452.
Abstract: This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.1452/_p

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@ARTICLE{e97-a_7_1452,
author={Tiebin WU, Hengzhu LIU, Botao ZHANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility},
year={2014},
volume={E97-A},
number={7},
pages={1452-1460},
abstract={This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.},
keywords={},
doi={10.1587/transfun.E97.A.1452},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - A Novel Test Data Compression Scheme for SoCs Based on Block Merging and Compatibility
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1452
EP - 1460
AU - Tiebin WU
AU - Hengzhu LIU
AU - Botao ZHANG
PY - 2014
DO - 10.1587/transfun.E97.A.1452
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2014
AB - This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.
ER -