135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki MOTOYOSHI; Naoko ONO; Kosuke KATAYAMA; Kyoya TAKANO; Minoru FUJISHIMA

doi:10.1587/transfun.E97.A.86

135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki MOTOYOSHI, Naoko ONO, Kosuke KATAYAMA, Kyoya TAKANO, Minoru FUJISHIMA

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Summary :

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.1 pp.86-93

Publication Date: 2014/01/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E97.A.86

Type of Manuscript: Special Section PAPER (Special Section on Wideband Systems)

Category: Implementation

Authors

Mizuki MOTOYOSHI
  Hiroshima University
Naoko ONO
  Toshiba Corporation
Kosuke KATAYAMA
  Hiroshima University
Kyoya TAKANO
  Hiroshima University
Minoru FUJISHIMA
  Hiroshima University

Keyword

CMOS, D-band, high-speed, wireless, ASK transceiver, short-millimeter-wave

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Mizuki MOTOYOSHI, Naoko ONO, Kosuke KATAYAMA, Kyoya TAKANO, Minoru FUJISHIMA, "135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset" in IEICE TRANSACTIONS on Fundamentals, vol. E97-A, no. 1, pp. 86-93, January 2014, doi: 10.1587/transfun.E97.A.86.
Abstract: An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.86/_p

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@ARTICLE{e97-a_1_86,
author={Mizuki MOTOYOSHI, Naoko ONO, Kosuke KATAYAMA, Kyoya TAKANO, Minoru FUJISHIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset},
year={2014},
volume={E97-A},
number={1},
pages={86-93},
abstract={An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.},
keywords={},
doi={10.1587/transfun.E97.A.86},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - 135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 86
EP - 93
AU - Mizuki MOTOYOSHI
AU - Naoko ONO
AU - Kosuke KATAYAMA
AU - Kyoya TAKANO
AU - Minoru FUJISHIMA
PY - 2014
DO - 10.1587/transfun.E97.A.86
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2014
AB - An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.
ER -