An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead

Shinnosuke YOSHIDA; Youhua SHI; Masao YANAGISAWA; Nozomu TOGAWA

doi:10.1587/transfun.E98.A.1406

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead

Shinnosuke YOSHIDA, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA

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As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1406-1418

Publication Date: 2015/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.1406

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Shinnosuke YOSHIDA
  Waseda University
Youhua SHI
  Waseda University
Masao YANAGISAWA
  Waseda University
Nozomu TOGAWA
  Waseda University

Keyword

timing-error prediction, robust design, delay variation, overclocking

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Shinnosuke YOSHIDA, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, "An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 7, pp. 1406-1418, July 2015, doi: 10.1587/transfun.E98.A.1406.
Abstract: As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1406/_p

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@ARTICLE{e98-a_7_1406,
author={Shinnosuke YOSHIDA, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead},
year={2015},
volume={E98-A},
number={7},
pages={1406-1418},
abstract={As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.},
keywords={},
doi={10.1587/transfun.E98.A.1406},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1406
EP - 1418
AU - Shinnosuke YOSHIDA
AU - Youhua SHI
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2015
DO - 10.1587/transfun.E98.A.1406
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.
ER -