Reference-Free Deterministic Calibration of Pipelined ADC

Takashi OSHIMA; Taizo YAMAWAKI

doi:10.1587/transfun.E98.A.665

Reference-Free Deterministic Calibration of Pipelined ADC

Takashi OSHIMA, Taizo YAMAWAKI

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Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.2 pp.665-675

Publication Date: 2015/02/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.665

Type of Manuscript: PAPER

Category: Analog Signal Processing

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Takashi OSHIMA, Taizo YAMAWAKI, "Reference-Free Deterministic Calibration of Pipelined ADC" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 2, pp. 665-675, February 2015, doi: 10.1587/transfun.E98.A.665.
Abstract: Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.665/_p

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@ARTICLE{e98-a_2_665,
author={Takashi OSHIMA, Taizo YAMAWAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reference-Free Deterministic Calibration of Pipelined ADC},
year={2015},
volume={E98-A},
number={2},
pages={665-675},
abstract={Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.},
keywords={},
doi={10.1587/transfun.E98.A.665},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - Reference-Free Deterministic Calibration of Pipelined ADC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 665
EP - 675
AU - Takashi OSHIMA
AU - Taizo YAMAWAKI
PY - 2015
DO - 10.1587/transfun.E98.A.665
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2015
AB - Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.
ER -