Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

Koichi FUJIWARA; Kazushi KAWAMURA; Masao YANAGISAWA; Nozomu TOGAWA

doi:10.1587/transfun.E99.A.1294

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

Koichi FUJIWARA, Kazushi KAWAMURA, Masao YANAGISAWA, Nozomu TOGAWA

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Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1294-1310

Publication Date: 2016/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.1294

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Koichi FUJIWARA
  Waseda University
Kazushi KAWAMURA
  Waseda University
Masao YANAGISAWA
  Waseda University
Nozomu TOGAWA
  Waseda University

Keyword

interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan

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Koichi FUJIWARA, Kazushi KAWAMURA, Masao YANAGISAWA, Nozomu TOGAWA, "Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 7, pp. 1294-1310, July 2016, doi: 10.1587/transfun.E99.A.1294.
Abstract: Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1294/_p

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@ARTICLE{e99-a_7_1294,
author={Koichi FUJIWARA, Kazushi KAWAMURA, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs},
year={2016},
volume={E99-A},
number={7},
pages={1294-1310},
abstract={Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.},
keywords={},
doi={10.1587/transfun.E99.A.1294},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1294
EP - 1310
AU - Koichi FUJIWARA
AU - Kazushi KAWAMURA
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2016
DO - 10.1587/transfun.E99.A.1294
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.
ER -