A Low Power-Consuming Embedded System Design by Reducing Memory Access Frequencies

Ching-Wen CHEN; Chih-Hung CHANG; Chang-Jung KU

doi:10.1093/ietisy/e88-d.12.2748

A Low Power-Consuming Embedded System Design by Reducing Memory Access Frequencies

Ching-Wen CHEN, Chih-Hung CHANG, Chang-Jung KU

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When an embedded system is designed, system performance and power consumption have to be taken carefully into consideration. In this paper, we focus on reducing the number of memory access times in embedded systems to improve performance and save power. We use the locality of running programs to reduce the number of memory accesses in order to save power and maximize the performance of an embedded system. We use shorter code words to encode the instructions that are frequently executed and then pack continuous code words into a pseudo instruction. Once the decompression engine fetches one pseudo instruction, it can extract multiple instructions. Therefore, the number of memory access times can be efficiently reduced because of space locality. However, the number of the most frequently executed instructions is different due to the program size of different applications; that is, the number of memory access times increases when there are less encoded instructions in a pseudo instruction. This situation results in a degradation of system performance and power consumption. To solve this problem, we also propose the use of multiple reference tables. Multiple reference tables will result in the most frequently executed instructions having shorter encoded code words, thereby improving the performance and power of an embedded system. From our simulation results, our method reduces the memory access frequency by about 60% when a reference table with 256 instructions is used. In addition, when two reference tables that contain 256 instructions each are used, the memory access ratio is 10.69% less than the ratio resulting from one reference table with 512 instructions.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.12 pp.2748-2756

Publication Date: 2005/12/01

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DOI: 10.1093/ietisy/e88-d.12.2748

Type of Manuscript: PAPER

Category: Computer Systems

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Ching-Wen CHEN, Chih-Hung CHANG, Chang-Jung KU, "A Low Power-Consuming Embedded System Design by Reducing Memory Access Frequencies" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 12, pp. 2748-2756, December 2005, doi: 10.1093/ietisy/e88-d.12.2748.
Abstract: When an embedded system is designed, system performance and power consumption have to be taken carefully into consideration. In this paper, we focus on reducing the number of memory access times in embedded systems to improve performance and save power. We use the locality of running programs to reduce the number of memory accesses in order to save power and maximize the performance of an embedded system. We use shorter code words to encode the instructions that are frequently executed and then pack continuous code words into a pseudo instruction. Once the decompression engine fetches one pseudo instruction, it can extract multiple instructions. Therefore, the number of memory access times can be efficiently reduced because of space locality. However, the number of the most frequently executed instructions is different due to the program size of different applications; that is, the number of memory access times increases when there are less encoded instructions in a pseudo instruction. This situation results in a degradation of system performance and power consumption. To solve this problem, we also propose the use of multiple reference tables. Multiple reference tables will result in the most frequently executed instructions having shorter encoded code words, thereby improving the performance and power of an embedded system. From our simulation results, our method reduces the memory access frequency by about 60% when a reference table with 256 instructions is used. In addition, when two reference tables that contain 256 instructions each are used, the memory access ratio is 10.69% less than the ratio resulting from one reference table with 512 instructions.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.12.2748/_p

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@ARTICLE{e88-d_12_2748,
author={Ching-Wen CHEN, Chih-Hung CHANG, Chang-Jung KU, },
journal={IEICE TRANSACTIONS on Information},
title={A Low Power-Consuming Embedded System Design by Reducing Memory Access Frequencies},
year={2005},
volume={E88-D},
number={12},
pages={2748-2756},
abstract={When an embedded system is designed, system performance and power consumption have to be taken carefully into consideration. In this paper, we focus on reducing the number of memory access times in embedded systems to improve performance and save power. We use the locality of running programs to reduce the number of memory accesses in order to save power and maximize the performance of an embedded system. We use shorter code words to encode the instructions that are frequently executed and then pack continuous code words into a pseudo instruction. Once the decompression engine fetches one pseudo instruction, it can extract multiple instructions. Therefore, the number of memory access times can be efficiently reduced because of space locality. However, the number of the most frequently executed instructions is different due to the program size of different applications; that is, the number of memory access times increases when there are less encoded instructions in a pseudo instruction. This situation results in a degradation of system performance and power consumption. To solve this problem, we also propose the use of multiple reference tables. Multiple reference tables will result in the most frequently executed instructions having shorter encoded code words, thereby improving the performance and power of an embedded system. From our simulation results, our method reduces the memory access frequency by about 60% when a reference table with 256 instructions is used. In addition, when two reference tables that contain 256 instructions each are used, the memory access ratio is 10.69% less than the ratio resulting from one reference table with 512 instructions.},
keywords={},
doi={10.1093/ietisy/e88-d.12.2748},
ISSN={},
month={December},}

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TY - JOUR
TI - A Low Power-Consuming Embedded System Design by Reducing Memory Access Frequencies
T2 - IEICE TRANSACTIONS on Information
SP - 2748
EP - 2756
AU - Ching-Wen CHEN
AU - Chih-Hung CHANG
AU - Chang-Jung KU
PY - 2005
DO - 10.1093/ietisy/e88-d.12.2748
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2005
AB - When an embedded system is designed, system performance and power consumption have to be taken carefully into consideration. In this paper, we focus on reducing the number of memory access times in embedded systems to improve performance and save power. We use the locality of running programs to reduce the number of memory accesses in order to save power and maximize the performance of an embedded system. We use shorter code words to encode the instructions that are frequently executed and then pack continuous code words into a pseudo instruction. Once the decompression engine fetches one pseudo instruction, it can extract multiple instructions. Therefore, the number of memory access times can be efficiently reduced because of space locality. However, the number of the most frequently executed instructions is different due to the program size of different applications; that is, the number of memory access times increases when there are less encoded instructions in a pseudo instruction. This situation results in a degradation of system performance and power consumption. To solve this problem, we also propose the use of multiple reference tables. Multiple reference tables will result in the most frequently executed instructions having shorter encoded code words, thereby improving the performance and power of an embedded system. From our simulation results, our method reduces the memory access frequency by about 60% when a reference table with 256 instructions is used. In addition, when two reference tables that contain 256 instructions each are used, the memory access ratio is 10.69% less than the ratio resulting from one reference table with 512 instructions.
ER -