A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

Konstantinos SIOZIOS; George KOUTROUMPEZIS; Konstantinos TATAS; Nikolaos VASSILIADIS; Vasilios KALENTERIDIS; Haroula POURNARA; Ilias PAPPAS; Dimitrios SOUDRIS; Antonios THANAILAKIS; Spiridon NIKOLAIDIS; Stilianos SISKOS

doi:10.1093/ietisy/e88-d.7.1369

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

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A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1369-1380

Publication Date: 2005/07/01

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DOI: 10.1093/ietisy/e88-d.7.1369

Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)

Category: Programmable Logic, VLSI, CAD and Layout

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Konstantinos SIOZIOS, George KOUTROUMPEZIS, Konstantinos TATAS, Nikolaos VASSILIADIS, Vasilios KALENTERIDIS, Haroula POURNARA, Ilias PAPPAS, Dimitrios SOUDRIS, Antonios THANAILAKIS, Spiridon NIKOLAIDIS, Stilianos SISKOS, "A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 7, pp. 1369-1380, July 2005, doi: 10.1093/ietisy/e88-d.7.1369.
Abstract: A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1369/_p

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@ARTICLE{e88-d_7_1369,
author={Konstantinos SIOZIOS, George KOUTROUMPEZIS, Konstantinos TATAS, Nikolaos VASSILIADIS, Vasilios KALENTERIDIS, Haroula POURNARA, Ilias PAPPAS, Dimitrios SOUDRIS, Antonios THANAILAKIS, Spiridon NIKOLAIDIS, Stilianos SISKOS, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications},
year={2005},
volume={E88-D},
number={7},
pages={1369-1380},
abstract={A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1369},
ISSN={},
month={July},}

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TY - JOUR
TI - A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications
T2 - IEICE TRANSACTIONS on Information
SP - 1369
EP - 1380
AU - Konstantinos SIOZIOS
AU - George KOUTROUMPEZIS
AU - Konstantinos TATAS
AU - Nikolaos VASSILIADIS
AU - Vasilios KALENTERIDIS
AU - Haroula POURNARA
AU - Ilias PAPPAS
AU - Dimitrios SOUDRIS
AU - Antonios THANAILAKIS
AU - Spiridon NIKOLAIDIS
AU - Stilianos SISKOS
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1369
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.
ER -