Low Latency Four-Flop Synchronizer with the Handshake Interface

Suk-Jin KIM; Jeong-Gun LEE; Kiseon KIM

doi:10.1093/ietisy/e88-d.7.1460

Low Latency Four-Flop Synchronizer with the Handshake Interface

Suk-Jin KIM, Jeong-Gun LEE, Kiseon KIM

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This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1460-1463

Publication Date: 2005/07/01

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Online ISSN

DOI: 10.1093/ietisy/e88-d.7.1460

Type of Manuscript: Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)

Category: Communications and Wireless Systems

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Suk-Jin KIM, Jeong-Gun LEE, Kiseon KIM, "Low Latency Four-Flop Synchronizer with the Handshake Interface" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 7, pp. 1460-1463, July 2005, doi: 10.1093/ietisy/e88-d.7.1460.
Abstract: This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1460/_p

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@ARTICLE{e88-d_7_1460,
author={Suk-Jin KIM, Jeong-Gun LEE, Kiseon KIM, },
journal={IEICE TRANSACTIONS on Information},
title={Low Latency Four-Flop Synchronizer with the Handshake Interface},
year={2005},
volume={E88-D},
number={7},
pages={1460-1463},
abstract={This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1460},
ISSN={},
month={July},}

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TY - JOUR
TI - Low Latency Four-Flop Synchronizer with the Handshake Interface
T2 - IEICE TRANSACTIONS on Information
SP - 1460
EP - 1463
AU - Suk-Jin KIM
AU - Jeong-Gun LEE
AU - Kiseon KIM
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1460
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.
ER -